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    2021-10-21 17:40:01
    Introduction to the Types of SDRAM


    Ⅰ Overview of SDRAM
    Ⅱ Types of SDRAM 1.SDRAM
    3.DDR2 SDRAM
    4.DDR3 SDRAM
    5.DDR4 SDRAM
    6.DDR5 SDRAM

    Ⅰ Overview of SDRAM

    We should first popularize the concept of RAM before discussing SDRAM's development history. RAM (Random Access Memory) is divided into two types: DRAM (dynamic RAM) and SRAM (static RAM).

    SDRAM (Asynchronous dynamic random access memory) and EDO DRAM (synchronous dynamic random access memory) are two DRAMs. We can classify them based on whether or not they are synced with the system clock.

    Let's talk about EDO DRAM for a while. Do you recall the 586 computers from the 1990s? It was the one that was eventually dubbed "Pentium." The screen mosaic was so vividly apparent because the 8M memory was fitted with 72-line EDO DRAM at the time. However, when compared to FPM DRAM, the performance of EDO DRAM has improved by 20% to 40%. This is due to the way it works, which is that when one piece of data is output, the next set of data is output at the same time. The so-called pre-processing mechanism is responsible for this.

    SDRAM was introduced later. There was a leap in comparison to preceding offerings, both in terms of size and frequency. SDRAM has typically gone through five mainstream development stages as of the beginning of 2020: SDRAM, DDR, DDR2, DDR3, DDR4, DDR5, and DDR6. DDR4 is still the most used memory type. The final international standard for DDR5 is still being developed due to the limited amount of samples available.

    The development of memory is largely tied to the progress of the CPU processor. Next, let's deal with it from generation to generation.

    Ⅱ Types of SDRAM


    The performance of EDO DRAM has been unable to meet its needs since the launch of Intel Celeron CPUs and AMD K6 processors, as well as associated motherboard chipsets. SDRAM swiftly takes the place of EDO DRAM. The synchronization of input and output signals with the system's external frequency improves SDRAM. SDRAM is popular due to the simplicity of having a bus width of 64 bits that corresponds to the processor's data bus width. It's worth noting that during this iterative period, the external bus frequency of the CPU processor rapidly grew from 100MHz to 133MHz due to a frequency disagreement between Intel and AMD, and the memory specification evolved from PC66 to PC100, PCIII.

    sdram board.jpg

    SDRAM board


    DDR SDRAM (hereafter referred to as "DDR") had twice the speed of SDRAM (that is, double rate SDRAM) in 2000, without a significant rise in production costs. And why is it possible for DDR to accomplish a twofold rate? This is due to the fact that DDR uses DLL delay-locked loop technology and a data filtering signal to allow the DDR controller to perform effective and precise data positioning. Simply put, DDR is able to read data from the clock's rising and falling edges. As a result, it can work twice as fast. Furthermore, because DDR employs the SSTL2 standard's 2,5V voltage, which is lower than SDRAM's LVTTL standard's 3.3V value, the power consumption is reduced.

    Of course, the standards take precedence over technology. During this time, memory standards evolved from PC133 to PC266, DDR333, DDR400 with 266MHz bandwidth, and DDR533 overclocking parameters.

    3.DDR2 SDRAM

    With the continuous improvement of CPU processor front-side bus bandwidth and the emergence of high-speed local buses, the performance of DDR has become a lock-throat technology that restricts processor performance. Therefore, in 2003, Intel announced the development plan of DDR2 SDRAM (hereinafter referred to as "DDR2").

    Compared to DDR, the biggest highlight of DDR2 is the reduction in power consumption. It benefits from the reduction in operating voltage, that is, from 2.5V to 1.8V, while increasing the operating frequency. How much has been increased?



    The operating frequency of DDR2 is about twice that of DDR. The pre-reading capacity of DDR2 is 4bit, and the memory pre-reading capacity of DDR is 2bit. The operating frequency makes DDR2 break through the 400MHz limit of DDR memory. Secondly, DDR2 uses different mechanisms for internal and external clocks. Specifically, the internal clock is 1/2 of the external clock, while DDR internal and external are the same. This also explains why DDR2 memory has different clock frequencies such as 400, 533, 667MHz while the capacity density is 512MB. The last point to say is that DDR2 abandons TSOP, which opens the door to memory FBGA packaging. It reduces parasitic capacitance and impedance matching problems and increases stability.

    4.DDR3 SDRAM

    In 2007, the JEDEC Association officially launched the DDR3 SDRAM (hereinafter referred to as "DDR3") specification, and DDR3 began to move on to the stage.

    Compared with DDR2, the working voltage of DDR3 is reduced from 1.8V to 1.5V and 1.35V (DDR3L), which further reduces power consumption and heat generation. DDR3 also adopts automatic self-refresh according to temperature, partial self-refresh, and other functions. To a certain extent, these functions make up for the shortcomings of DDR3's longer delay time. At the same time, the speed of DDR3 starts from 800MHz and can reach a maximum of 1600MHz, which is almost twice the speed of DDR2. How is this achieved? Because DDR3 can output 8 bits of data in one clock cycle. The amount of data transfer per unit time is twice that of DDR2. In addition, the pre-read capability of DDR3 is 8bit, which is twice that of DDR2, making the core operating frequency of DDR3 only 1/8 of the external frequency.

    5.DDR4 SDRAM

    At the end of 2014, DDR4 memory products with a take-off frequency of 2133MHz were on the market. This marked the arrival of the DDR4 era. As of today, DDR4 still occupies the mainstream position in the market.



    Compared with DDR3, in terms of power consumption, the operating voltage of DDR4 has dropped from 1.5V to 1.2V and 1.05V (DDR4L), which means more power-saving and less heat generation. In terms of speed, starting from 2133MHz, the highest speed can reach 4266MHz, which is close to three times that of DDR3. How is this achieved?

    First of all, let’s talk about the transmission mechanism. In addition to supporting traditional SE signals, DDR4 also introduces differential signal technology. In other words, it has evolved to the stage of a two-way transmission mechanism. Secondly, DDR4 adopts a point-to-point design that implifies the memory module, which is easier to achieve high frequency. Finally, DDR4 adopts three-dimensional stacked packaging technology to increase the capacity of the unit chip and also adopts temperature compensation self-refresh, temperature-compensated automatic refresh, and data bus inversion technology, which reduces the power consumption.

    The competition between Intel and AMD is intensifying. Now desktop computers are starting to take off with 6 cores. It is foreseeable that memory performance will soon become a new bottleneck. Therefore, the JEDEC Association began to work with major SDRAM manufacturers as early as 2017 to draft the DDR5 standard. In 2018, the JEDEC Association announced the DDR5 technical specification draft. On February 19, 2019, JEDEC announced the updated LPDDR5 standard, but it has not yet Launch the official version. Next, Let's look at the difference between DDR5 and DDR4 from a technical point of view.

    6.DDR5 SDRAM

    The larger capacity, higher speed, new functions, and new features are the obvious improvements of DDR5 SDRAM (hereinafter referred to as "DDR5") from DDR4.

    According to the draft proposed by JEDEC, in terms of capacity, the capacity of a single DDR5 is from 8Gb to 64Gb. In terms of speed, DDR5 starts from 3.2Gbps to 6.6Gbps and can expand up to 8.4Gbps. The prefetch data capacity increases from 8n of DDR4 to 16n. The burst data length becomes 16. In terms of power consumption, the working voltage of DDR5 is from 1.2V of DDR4 to 1.1V. In addition, in terms of functions, DDR5 has inherited activation, reading and writing, precharge, refresh, self-refresh, power saving mode, ZQ calibration, and many other new functions, or new features.



    6.1 Command and address signals share the CA bus

    DDR5 is the first time in the history of memory technology to synthesize command and address signals into a CA bus.

    Compared with the independent characteristics of the command and address signal pins in previous memory products, the resolution of DDR5 is very different. Specifically, when DDR4 and previous memory products are working, under the premise that the chip select signal is valid, when the rising edge comes, the DRAM command receiver will sample all command signals to parse the current command and sample the address signal as needed to obtain address information. This means that all operations are in one clock cycle. Since DDR5 uses the CA bus, many commands require two clock cycles to complete. When the first rising edge comes, the CA signal is first sampled to analyze the command, and then when the second rising edge comes, another sample CA signal is taken to resolve the address.

    Does this process increase the complexity of the analysis? To be honest, yes. Due to the increase in capacity and speed, the number of address signals will also increase. This is not difficult to understand, just as if there are more workers, a few more dormitories must be provided. Taking into account the requirements of high-speed transmission, the number of gold fingers in DDR5 memory modules will also increase with the increase of VDD pins to meet the shortest current return path requirements. Let's imagine, as the number of gold fingers increases, does the size increase? This violated the trend theorem of miniaturization of electronic products, so the CA bus was chosen. Therefore, the original requirement of more than 300 golden finger pins was reduced to 14 CA pins. From then on, the number of pins and the number of solder balls kept consistent with DDR4.

    6.2 2N mode

    What is 2N mode? In fact, it is to match the above-mentioned command input method that requires two consecutive cycles to complete. The 2N mode control bit determines the specific CA bus sampling interval.

    6.3 Add decision feedback equalizer DFE

    Why introduce decision feedback equalizer DFE in DQ receiver? When the data rate exceeds 3.2Gbps, the inter-symbol crosstalk ISI will increase, and the reduction of the signal-to-noise ratio may cause the eye diagram at the DRAM solder ball to be completely closed. The maximum data rate of DDR5 can reach 8.4Gbps, so some means must be taken to solve this problem. The current method is to add some kind of equalizer to improve the eye pattern, such as the one gain amplifier proposed in the draft DDR5 specification, 1 DFE adder, 4 DQ slicers, and 1 parameter multiplier that constitute a four-tap DFE.

    6.4 Low power consumption

    Power consumption has always been the focus of memory performance. Nobody wants to spend money to buy a hot device. For DDR5, it has inherited many features of LPDDR4, such as expanding the mode register to 256, adding the mode register read command MRR and multi-purpose command MPC, so as to realize interface initialization, training, periodic calibration, and other functions.

    6.5 Loopback mode

    It was the same high speed that led to the birth of the loopback mode, so why not talk about it before power consumption? This is because the loopback mode is mainly used in testing. It is to test the bit error rate, so as to judge the performance of the receiver. Those who have studied software know that we usually use the write-read method to test the receiver. But, when the rate is as high as 8.4Gbps, the internal space of the DRAM will not be enough, and the test time will be very long.

    In order to improve test stability and test efficiency, technicians have proposed a loopback mode. It allows DDR5 to directly return the test data sent by the memory controller or the driver of the test device to its receiver. But all things come at a price. Adding LBDQS (single-ended DQS signal), LBDQ (DQ signal) pins and mode registers is what DDR5 needs to pay. The former returns the received data to the opposite side. The latter controls the data received by the DDR5 corresponding pin back to the sender.

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